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Controlling Transaction Input into CICS/TS |
September 11, 2006 |
| Controlling the number of transactions entering into CICS/TS is an
important tuning area. Allowing a larger volume than can be
handled by CICS/TS can result in Short on Storage (SOS)
conditions and create a lack of other resources such as strings.
However, reaching the maximum task limit can also have the
negative effect of creating an “artificial bottleneck” when resources
are available. In both cases, response times are negatively
affected. An artificial bottleneck is one that causes a delay when
there are sufficient resources available to handle the tasks. This
article reviews two important user controls available to control the
transaction flow into CICS/TS and possible causes for the MXT limit
to be reached. |
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CICS/TS and SOS Conditions |
June 23, 2006 |
| Since its inception in 1969 as an IBM product, CICS performance and reliability has always been sensitive to the availability of resources such as CPU processor capacity, I/O response and availability of storage, both real and virtual. However, of all the resources, the availability of virtual storage is probably the most important and can be referred to as the “Achilles Heel” of CICS. The lack of virtual storage can result in system outage or the infamous Short on Storage (SOS) condition. CICS outages due to a lack of virtual storage result from an operating system type GETMAIN failure. SOS conditions can occur due to lack of virtual storage in the CICS dynamic storage areas either above or below the line. Over the years CICS has been enhanced and rearchitected with some major improvements being made in the way CICS handles virtual storage. This article addresses the improvements made and what can be done to resolve virtual storage problems that affect CICS/TS performance, reliability and availability. |
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Tuning Temporary Storage in CICS/TS |
March 13, 2006 |
| Temporary Storage (TS) is being used more frequently in CICS/TS for both temporary and permanent information. This article reviews important TS tuning areas that have to be addressed to get better response times. |
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CICS/TS and TCB Switching |
March 10, 2006 |
| With the advent of open application interface support in CICS/TS, TCB switching has become an important tuning concern. This article explores what causes TCB switching and what can be done to reduce the CPU overhead associated with incorrect use of this feature. |
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z/OS Workload Manager and CICS/TS MXT |
March 9, 2006 |
| The major concern with the setting of the maximum tasks (MXT) parameter in older CICS versions was the amount of pre-allocated virtual storage required to support the number selected. However, with the implementation of the Workload Manager, this concern has expanded to include CPU overhead. This article explores the considerations necessary when establishing the MXT value. |
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Tuning CICS/TS LSR Pools |
March 9, 2006 |
| Eliminating I/O is the major tuning objective when optimizing CICS. VSAM files should be defined in LSR to obtain the best look-aside hit ratio that result in improved response time and lower CPU utilization. |
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Tuning the VSAM KSDS Index CISZ |
November 22, 2004 |
| Incorrect specification of the index CISZ can result in wasted space and premature CA splits. This article explains this phenomena and how and why it can/should be corrected. |
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Selecting the Number of Strings for VSAM File under CICS/TS |
October 16, 2004 |
| Allocating the correct number of strings can have a positive effect in improving response time without having to over allocate virtual and real storage requirements. This article explores how to allocate strings for VSAM files under CICS/TS. |
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Analyzing Non-Shared Resource Files (NSR) Files |
October 15, 2004 |
| Why are you using NSR files in CICS/TS? This article explores the look-aside capacity associated with NSR and why you should consider LSR. |
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Setting the Interval Control Values in CICS/TS |
August 19, 2004 |
| There are several important System Initialization Table (SIT) parameters used to set certain clock values that are used by CICS during execution. Incorrect settings of these values can result in CPU overhead. This article reviews how to set these timer values. |
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